Implementation of a Low Latency Motion Estimator for HEVC Encoder on FPGA

ESTEFANIA, ALCOCER and MANUEL, P. MALUMBRES and OTONIEL, LOPEZ-GRANADO and ROBERTO, GUTIERREZ (2015) Implementation of a Low Latency Motion Estimator for HEVC Encoder on FPGA. In: Third International Conference on Advances in Information Processing and Communication Technology - IPCT 2015, 10-11 December, 2015, Rome, Italy.

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Abstract

HEVC is the latest video coding standard aimed to compress double to that its predecessor standard H.264. Motion Estimation is one of the critical parts in the encoder due to the introduction of asymmetric motion partitioning and higher size of coding tree unit. In this paper, a design for an Integer Motion Estimator of HEVC is presented over specific hardware architecture for real time implementation. The implementation shows a new IME unit supporting asymmetric partitioning mode which significantly reduce the overall motion estimation processing time. The prototyped architecture has been designed in VHDL, synthesized and implemented using the Xilinx FPGA, Zynq-7000 xc7z020 clg484-1. The proposed design is able to process 30 fps at Full- HD and 15 fps at 2K resolution.

Item Type: Conference or Workshop Item (Paper)
Uncontrolled Keywords: HEVC, video coding, FPGA, motion estimation.
Depositing User: Mr. John Steve
Date Deposited: 04 Apr 2019 11:58
Last Modified: 04 Apr 2019 11:58
URI: http://publications.theired.org/id/eprint/1150

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