Predictable CPU Architecture Designed for Small Real-Time Applications – Implementation Results

IONEL, ZAGAN and VASILE, GHEORGHITA GAITAN (2015) Predictable CPU Architecture Designed for Small Real-Time Applications – Implementation Results. In: Third International Conference on Advances in Computing, Electronics and Communication - ACEC 2015, 10-11 October, 2015, Zurich, Switzerland.

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Abstract

The purpose of this paper is to describe and present the implementation results of nMPRA-MT processor concept designed for small real-time applications. Our target is to validate a fine-grained multithreading CPU architecture that uses replication and remapping techniques for the program counter, general purpose registers and pipeline registers. The new predictable CPU implementation is based on a hardware scheduler engine, being able to schedule dynamically a set of tasks on the five-stage pipeline assembly line. Using a FPGA device from Xilinx, we validate the innovative nMPRA-MT processor, interleaving different types of threads into the pipeline assembly line, providing predictability and hardware-based isolation for hard real-time threads. Mechanisms for synchronization and inter-task communication are also taken into consideration.

Item Type: Conference or Workshop Item (Paper)
Uncontrolled Keywords: predictable; real-time systems; fine-grained multithreading; hardware scheduler; pipeline; hard real-time
Depositing User: Mr. John Steve
Date Deposited: 20 Apr 2019 11:35
Last Modified: 20 Apr 2019 11:35
URI: http://publications.theired.org/id/eprint/1413

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