Implementation and Execution of Math Partial Reconfiguration Region and LED Dealing with Xilinx PlanAhead

IPSEETA, NANDA and S M, ALI (2015) Implementation and Execution of Math Partial Reconfiguration Region and LED Dealing with Xilinx PlanAhead. In: Fourth International Conference On Advances in Computing, Electronics and Electrical Technology - CEET 2015, 26-27 September, 2015, Kuala Lumpur, Malaysia.

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Abstract

Dynamic Partial Reconfiguration (DPR) of Field Programmable Gate Array (FPGA) was introduced to overcome the need for more resources on the FPGA.PDR could change the functionality and efficiency of the system in order to accommodate more hardware module, save power and fabric area.PDR involves the design of modules that are independent of each other so that they can be loaded in the same fabric area one after other. In this paper the authors reconfigure some specific region of the FPGA with a new functionality at run time while the remaining areas remain static during this time. The complexities during the runtime can be simplified by a tool called PLANAHEAD which was introduced by XILINX that is able to implement during runtime reconfigurable systems for all VIRTEX field programmable gate array. PLANAHEAD is the first graphical environment for partial reconfiguration which gives the flexibility for reducing the board space, change a design in the field and also reduces the power consumption.

Item Type: Conference or Workshop Item (Paper)
Uncontrolled Keywords: Dynamic Partial Reconfiguration (DPR), Field Programmable Gate Array (FPGA), PLANAHEAD
Depositing User: Mr. John Steve
Date Deposited: 26 Apr 2019 04:42
Last Modified: 26 Apr 2019 04:42
URI: http://publications.theired.org/id/eprint/1527

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