Improved High Speed, Low Power CMOS Multiplier

ALAA, HUSSEIN and AMEEN, BIN OBADI (2015) Improved High Speed, Low Power CMOS Multiplier. In: Third International Conference on Advances in Computing, Electronics and Electrical Technology - CEET 2015, 11-12 APRIL 2015, Kuala Lumpur, Malaysia.

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Abstract

A high speed four quadrant current mode multiplier is presented. It is based on CMOS devices arranged in dual trans-linear loops and working in saturation region. The designed circuit operates under the voltage supply of ±1.5V. Design simulation was carried out using Tanner EDA Tools v13.0 with level 49 parameters (BSIM3 v3.1) in 0.35μm standard CMOS technology. Simulation results show that the multiplier has a 3dB bandwidth of 440MHz, linearity error of 1.1% and maximum power consumption of 158μW. The analog multiplier is used to carry out amplitude modulation whose results are also reported.

Item Type: Conference or Workshop Item (Paper)
Uncontrolled Keywords: CMOS multiplier; translinear loop; current mode; squarer circuit; four quadrant.
Depositing User: Mr. John Steve
Date Deposited: 07 May 2019 10:10
Last Modified: 07 May 2019 10:10
URI: http://publications.theired.org/id/eprint/1959

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