Design and Implementation of MC-CDMA Wireless Communication System Using Partial Reconfiguration in FPGA—A Review

ALI KAREEM, NAHAR and YUSNITA, RAHAYU (2015) Design and Implementation of MC-CDMA Wireless Communication System Using Partial Reconfiguration in FPGA—A Review. In: Third International Conference on Advances in Computing, Electronics and Electrical Technology - CEET 2015, 11-12 APRIL 2015, Kuala Lumpur, Malaysia.

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this paper reviews the state of the technique of field programmable gate array (FPGA) for partial Reconfiguration (PR), design methodologies of Wireless Communication System, such as Multi Carrier Code Division Multiple Access (MC-CDMA) technique has been to be suited for future wireless systems that are expected to provide higher data rates and greater flexibility for the services of voice, data, video and Internet to the users due to its property in using the bandwidth in efficient manner. The Software Defined Radio is considered as a wireless system applied by routines so as software. Consequently, the use of SDR allows vehicle manufacturers to familiarize communication applications sustained through cars to appropriate to the standards of the respected country presented in the object oriented programming. FPGAs are playing a very significant role in SDR. However, in modern wireless communication system programs, SDR and CR need to design a wide range of waveforms complex, which it is complicated in design and performance and implementation needs more time. The design of the modulation and demodulation and other signal processing application of PR technique that have the ability to modify blocks of logic dynamically by downloading partial bit files, while the remaining logic is still working without interruption; thus, power consumption and configuration time can be saved for a larger extent. The PR using was allowed to move for fewer or smaller devices as, decrease power and increase system upgradability.

Item Type: Conference or Workshop Item (Paper)
Uncontrolled Keywords: MC-CDMA, SDR, FPGA, PR, and VHDL
Depositing User: Mr. John Steve
Date Deposited: 07 May 2019 10:10
Last Modified: 07 May 2019 10:10

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