High performance gate-stack fabrication process of Ge-MOS structure for future electronic devices

HARUKA, FUJIWARA and HIROSHI, YAMADA and MITARO, NAMIKI and TOMO, UENO and YOSHITAKA, IWAZAKI (2018) High performance gate-stack fabrication process of Ge-MOS structure for future electronic devices. In: Eighth International Conference On Advances in Computing, Electronics and Electrical Technology - CEET 2018, 03-04 February, 2018, Kuala Lumpur, Malaysia.

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Si has been widely used as primary semiconductor materials for electronic device fabrication. Due to the limitation of its electrical properties such as electron and hole mobilities, however, Ge would be one of the candidates for future electronic device materials because of its higher mobilities of both carriers. However, since GeO2 which composed of Ge-O chemical bonds is known to have water solubility and it reacts with Ge substrates at high temperature, it is well known that GeO desorption occurs at GeO2/Ge interface during higher temperature annealing, as well as during the course of higher temperature oxidation process itself. In this research, we attempted to improve interface characteristics by depositing Hf on the GeO2/Ge structure and applying heat treatment (PMA: Post Metallization Annealing). As a result, it is clearly shown that the decrease of Dit value by the PMA, and the leakage current was reduced and insulating property was improved by applying PMA. We consider that a slight amount of Hf buried the GeO2 film by Hf-PMA and the bonding strength of Ge-O became stable. It was confirmed that Hf-PMA is effective for GeO2/Ge stacked structure as a solution to reduce the Dit values.

Item Type: Conference or Workshop Item (Paper)
Uncontrolled Keywords: Ge, GeO2, MOS, Hf, PMA
Depositing User: Mr. John Steve
Date Deposited: 10 Mar 2019 09:18
Last Modified: 10 Mar 2019 09:18
URI: http://publications.theired.org/id/eprint/230

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