A chip ID generation circuit – latch based

ALEXANDRA, STANCIU and FLORIN, MOLDOVEANU and MARIUS, TUDORANCEA (2014) A chip ID generation circuit – latch based. In: International Conference on Advances in Information Processing and Communication Technology - IPCT 2014, 07- 08 June,2014, Rome, Italy.

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In this paper, we introduce a chip ID generation circuit, which uses process variations, that appear during the physical execution of an FPGA. In [1] Gassend et al. introduced for the first time the ROs digital circuit with the aim of emphasizing the uncontrollable effect of silicon process variations at the delay of the digital component interconnection. After that, different constructions based on process variations start to appear. The digital circuit analyzed is a modification of the latch based circuit with the scope to minimizing the hardware resource usage and to fit an FPGA implementation. We also introduce a new statistic assessment method based on Kolmogorov-Smirnov test for the inter-distance and the intra-distance analysis. The chip ID generation circuit could produce FPGA secret keys that deal with the security issues such as: cloning, overproducing or stealing the implemented applications on FPGA.

Item Type: Conference or Workshop Item (Paper)
Uncontrolled Keywords: process variation, latch, FPGA, chip ID
Depositing User: Mr. John Steve
Date Deposited: 20 May 2019 12:09
Last Modified: 20 May 2019 12:09
URI: http://publications.theired.org/id/eprint/2527

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