A New Technique For Designing Low Power 2-Bit Magnitude Comparator

K. G., SHARMA, and TRIPTI, SHARMA, and VIJAYA, SHEKHAWAT (2014) A New Technique For Designing Low Power 2-Bit Magnitude Comparator. In: International Conference on Advances In Engineering And Technology - ICAET 2014, 24 - 25 May, 2014, RIT, Roorkee, India.

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Abstract

In this paper a new logic technique and hence circuit design has been proposed for the implementation of magnitude comparator. This proposed 2-Bit magnitude comparator is design to improve power consumption as well as on-chip area than its peer design. The proposed 2-Bit magnitude comparator has threshold loss of 13%-20%. This threshold loss is due to PTL (Pass Transistor Logic) logic applied at the input end and at the output end TG (Transmission Gate) logic is used, this is done to reduce the number of transistor. The schematic of 2-Bit magnitude comparator is designed using Tanner EDA Tool version 12.6 at 45nm technology.

Item Type: Conference or Workshop Item (Paper)
Uncontrolled Keywords: Magnitude Comparator, TG logic, Proposed Technique and Low Power
Depositing User: Mr. John Steve
Date Deposited: 21 May 2019 11:44
Last Modified: 21 May 2019 11:44
URI: http://publications.theired.org/id/eprint/2612

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