Power and Delay Optimization of 1 Bit Full Adder using MTCMOS Technique

GAURAV, SONI and SONAM, GOUR and SWATI, S.KUMAR (2014) Power and Delay Optimization of 1 Bit Full Adder using MTCMOS Technique. In: International Conference on Advances In Engineering And Technology - ICAET 2014, 24 - 25 May, 2014, RIT, Roorkee, India.

[img]
Preview
Text
20140726_095228.pdf - Published Version

Download (604kB) | Preview
Official URL: https://www.seekdl.org/conferences/paper/details/3...

Abstract

In this paper, a 28T full adder using MTCMOS technique design is proposed. Combinational logic has extensive applications in quantum computing, low power VLSI design and optical computing. Reducing power dissipation is one of the most principle subjects in VLSI design today. The subthreshold leakage current becomes a large component of total power dissipation. Low- power design techniques proposed to minimize the active leakage power in nanoscale CMOS very large scale integration (VLSI) systems. In this paper the active power and delay of full adder is analyzed with or without MTCMOS. The power and delay evaluation has been carried out using extensive simulation on the HSPICE circuit simulator. The simulation results are based on 32nm and 45nm Berkeley Predictive Technology Model (BPTM). By using MTCMOS technique in full adder a reduction is observed in the active power is 98.3% in 32nm and 99.1% in 45nm. The reduction in the delay is the 21% for sum output and 25% for carry output in 32nm. In 45nm the reduction in delay is 26% for sum output and 29% for carry output.

Item Type: Conference or Workshop Item (Paper)
Uncontrolled Keywords: Full Adder, low power, CMOS circuits, MTCMOS, Subthreshold leakage current, simulation
Depositing User: Mr. John Steve
Date Deposited: 24 May 2019 12:29
Last Modified: 24 May 2019 12:29
URI: http://publications.theired.org/id/eprint/2636

Actions (login required)

View Item View Item