1.5 Bit/Stage, 12-Bit Pipeline ADC Design with Foreground Calibration

ECE, OLCAY GUNES and LIDA, KOUHALVANDI and SERCAN, AYGUN (2017) 1.5 Bit/Stage, 12-Bit Pipeline ADC Design with Foreground Calibration. In: Sixth International Conference on Advances in Computing, Electronics and Communication - ACEC 2017, 09-10 December, 2017, Rome, Italy.

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Abstract

In this paper, 12-Bit pipeline ADC is to be designed together with caring non-idealities. Pipeline issue in modern computers is quite advantageous for performance. Such structure can be constructed in analog-to-digital converters to make the performance faster. By considering the non-ideal cases for the design, more realistic outputs are expected. There are several non-ideal effects that lower the ADC performance such as gain error and capacitor mismatches. By using calibration techniques like background or foreground calibration, non-ideal effects can be reduced. In this paper, foreground calibration technique is applied and tabloid results are presented at the end. Modelling of the pipeline ADC is constructed on Matlab Simulink environment.

Item Type: Conference or Workshop Item (Paper)
Uncontrolled Keywords: ADC, data converter, foreground, non-idealities, pipeline, sample and hold
Depositing User: Mr. John Steve
Date Deposited: 10 Mar 2019 09:30
Last Modified: 10 Mar 2019 09:30
URI: http://publications.theired.org/id/eprint/299

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