Design and Performance Comparison of 7-level Diode Clamped Multilevel Inverter for Modified SVPWM Techniques

CH., LOKESHWAR REDDY and M., SUSHAMA and P. SATISH, KUMAR (2017) Design and Performance Comparison of 7-level Diode Clamped Multilevel Inverter for Modified SVPWM Techniques. In: Sixth International Conference on Advances in Computing, Control and Networking - ACCN 2017, 25-26 February 2017, Bangkok, Thailand.

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Abstract

In this paper, a 7-level Diode Clamped Multilevel Inverter (DCMLI) is simulated with three different carrier PWM techniques. Here, Carrier based Sinusoidal Pulse Width Modulation (SPWM), Third Harmonic Injected Pulse Width Modulation (THIPWM) and Modified Carrier-Based Space Vector Pulse Width Modulation (SVPWM) are used as modulation strategies. These modulation strategies include Phase Disposition technique (PD), Phase Opposition Disposition technique (POD), and Alternate Phase Opposition Disposition technique (APOD). In all the modulation strategies triangular carrier and trapezoidal triangular carrier signals are compared with reference signal and control pulses are generated. The detailed analysis of the results has been presented and studied in terms of fundamental component of output voltage and THD.

Item Type: Conference or Workshop Item (Paper)
Uncontrolled Keywords: DCMLI, PDSVPWM, PODSVPWM,APODSVPWM.
Depositing User: Mr. John Steve
Date Deposited: 16 Mar 2019 12:29
Last Modified: 16 Mar 2019 12:29
URI: http://publications.theired.org/id/eprint/556

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